Advanced Packaging

confovisSolutionsAdvanced Packaging

Advanced packaging is a subset of semiconductor packaging that uses novel techniques and materials to increase integrated circuits’ performance, power, modularity, and durability.

Semiconductor packaging


Semiconductor packaging refers to the last steps of the manufacturing of integrated circuits (IC) or micro electromechanical systems (MEMS). Packaging is an intermediate stage between the manufacturing of chips on semiconductor wafers and their incorporation them into electronic devices such as smartphones.

The scope of semiconductor packaging is twofold: 

  1. It protects the ICs from physical damage like mechanical impact, chemical contamination, radiation, heat, and light exposure. 
  2. It connects the ICs to the external environment (e.g. PCB) via balls, wires or pins.

Advanced packaging for heterogeneous integration


Advanced packaging technologies include high-density fanout wafer-level packaging (WLP), 2.5D IC, and 3D IC. These technologies are also referred to as heterogeneous integration.

The market is pushing towards packing more functionalities into smaller devices. This requires higher integration capabilities and interconnect densities leading to smaller bump sizes. Controlling the bump height is critical to ensure reliable connections between stacked components. It is also important to determine the size and position of each bump. 

Our Solutions for Advanced Packaging

100% bump inspection in advanced packaging

Both 2D and 3D metrology are required for bump inspection in advanced packaging. Application fields with high reliability requirements like aerospace, automotive, and defense rely on zero defect manufacturing. A 100% bump inspection is thus fundamental. If one single bump fails, the whole device fails.

A complete wafer inspection allows to determine various types of defects including cluster defects, indicating equipment or process-related issues, and repeating defects, indicating mask or reticle issues. In both cases a sampled inspection approach may miss these issues. Hence the importance of a 100% wafer bump inspection and metrology. 




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